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-- Company: 
-- Engineer: 
-- 
-- Create Date: 06/08/2025 10:16:38 AM
-- Design Name: 
-- Module Name: sevenSementDis - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sevenSementDis is
    Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);
           C : out STD_LOGIC;
           SevenSD : out STD_LOGIC_VECTOR (6 downto 0));
end sevenSementDis;

architecture Behavioral of sevenSementDis is

begin
C <= '0';
process(SW)
begin
case (SW) is
    when "0000" => SevenSD <= "0111111"; 
    when "0001" => SevenSD <= "0000110"; 
    when "0010" => SevenSD <= "1011011";
    when "0011" => SevenSD <= "1001111"; 
    when "0100" => SevenSD <= "1100110"; 
    when "0101" => SevenSD <= "1101101"; 
    when "0110" => SevenSD <= "1111101"; 
    when "0111" => SevenSD <= "0000111"; 
    when "1000" => SevenSD <= "1111111"; 
    when "1001" => SevenSD <= "1101111"; 
    when others => SevenSD <= "1000000"; 
end case;
end process;
end Behavioral;
