Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version     : Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
| Date             : Sun Jun  8 11:59:27 2025
| Host             : Balerion running 64-bit major release  (build 9200)
| Command          : report_power -file sevenSementDis_power_routed.rpt -pb sevenSementDis_power_summary_routed.pb -rpx sevenSementDis_power_routed.rpx
| Design           : sevenSementDis
| Device           : xc7z020clg400-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
----------------------------------------------------------------------------------------------------------------------------------------------------------------

Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+---------------------------------+
| Total On-Chip Power (W)  | 8.237 (Junction temp exceeded!) |
| Design Power Budget (W)  | Unspecified*                    |
| Power Budget Margin (W)  | NA                              |
| Dynamic (W)              | 7.363                           |
| Device Static (W)        | 0.875                           |
| Effective TJA (C/W)      | 11.5                            |
| Max Ambient (C)          | 0.0                             |
| Junction Temperature (C) | 120.0                           |
| Confidence Level         | Low                             |
| Setting File             | ---                             |
| Simulation Activity File | ---                             |
| Design Nets Matched      | NA                              |
+--------------------------+---------------------------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+----------------+-----------+----------+-----------+-----------------+
| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic    |     0.022 |        8 |       --- |             --- |
|   LUT as Logic |     0.022 |        4 |     53200 |           <0.01 |
|   Others       |     0.000 |        1 |       --- |             --- |
| Signals        |     0.059 |       11 |       --- |             --- |
| I/O            |     7.282 |       12 |       125 |            9.60 |
| Static Power   |     0.875 |          |           |                 |
| Total          |     8.237 |          |           |                 |
+----------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.347 |       0.097 |      0.250 |
| Vccaux    |       1.800 |     0.353 |       0.266 |      0.087 |
| Vcco33    |       3.300 |     2.058 |       2.057 |      0.001 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.018 |       0.000 |      0.018 |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccpint   |       1.000 |     0.387 |       0.000 |      0.387 |
| Vccpaux   |       1.800 |     0.010 |       0.000 |      0.010 |
| Vccpll    |       1.800 |     0.003 |       0.000 |      0.003 |
| Vcco_ddr  |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco_mio0 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco_mio1 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+----------------+-----------+
| Name           | Power (W) |
+----------------+-----------+
| sevenSementDis |     7.363 |
+----------------+-----------+


