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-- Company: 
-- Engineer: 
-- 
-- Create Date: 06/22/2025 11:55:44 AM
-- Design Name: 
-- Module Name: TestBench - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TestBench is
--  Port ( );
end TestBench;

architecture Behavioral of TestBench is
    component FourBitRegister
        port(
            clk : in STD_LOGIC;
            d   : in STD_LOGIC_VECTOR (3 downto 0);
            q   : out STD_LOGIC_VECTOR (3 downto 0)
        );
    end component;

    signal clk : STD_LOGIC := '0';
    signal d   : STD_LOGIC_VECTOR (3 downto 0) := "0000";
    signal q   : STD_LOGIC_VECTOR (3 downto 0);
    constant clk_PERIOD : time := 10 ns;

begin
    uut: FourBitRegister PORT MAP(  -- Instantiate the Unit Under Test
        clk => clk,
        d   => d,
        q   => q
    );

    clk_PROCESS: process
    begin
        clk <= '0';
        wait for clk_PERIOD/2;
        clk <= '1';
        wait for clk_PERIOD/2;
    end process;

    stim_proc: process
    begin
        wait for 100 ns;
        -- insert stimulus here
        d <= "0001"; wait for 20 ns;
        d <= "0010"; wait for 20 ns;
        d <= "0011"; wait for 20 ns;
        d <= "0100"; wait for 20 ns;
        d <= "0101"; wait for 20 ns;
        d <= "0110"; wait for 20 ns;
        d <= "0111"; wait for 20 ns;
        d <= "1000"; wait for 20 ns;
        d <= "1001"; wait for 20 ns;
        d <= "1010"; wait for 20 ns;
        d <= "1011"; wait for 20 ns;
        d <= "1111"; wait for 20 ns;
        wait;
    end process;
end Behavioral;
