Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
| Date         : Sun Jun 22 12:03:31 2025
| Host         : Balerion running 64-bit major release  (build 9200)
| Command      : report_methodology -file FourBitRegister_methodology_drc_routed.rpt -pb FourBitRegister_methodology_drc_routed.pb -rpx FourBitRegister_methodology_drc_routed.rpx
| Design       : FourBitRegister
| Device       : xc7z020clg400-1
| Speed File   : -1
| Design State : Fully Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 4
+-----------+------------------+-----------------------------+------------+
| Rule      | Severity         | Description                 | Violations |
+-----------+------------------+-----------------------------+------------+
| TIMING-17 | Critical Warning | Non-clocked sequential cell | 4          |
+-----------+------------------+-----------------------------+------------+

2. REPORT DETAILS
-----------------
TIMING-17#1 Critical Warning
Non-clocked sequential cell  
The clock pin q_reg[0]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#2 Critical Warning
Non-clocked sequential cell  
The clock pin q_reg[1]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#3 Critical Warning
Non-clocked sequential cell  
The clock pin q_reg[2]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#4 Critical Warning
Non-clocked sequential cell  
The clock pin q_reg[3]/C is not reached by a timing clock
Related violations: <none>


