#-----------------------------------------------------------
# Vivado v2019.2 (64-bit)
# SW Build 2708876 on Wed Nov  6 21:40:23 MST 2019
# IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
# Start of session at: Sun Jun 22 12:02:49 2025
# Process ID: 5100
# Current directory: C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1
# Command line: vivado.exe -log FourBitRegister.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FourBitRegister.tcl -notrace
# Log file: C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1/FourBitRegister.vdi
# Journal file: C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source FourBitRegister.tcl -notrace
Command: link_design -top FourBitRegister -part xc7z020clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z020clg400-1
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 631.707 ; gain = 0.000
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.srcs/constrs_1/new/contraint_4.xdc]
Finished Parsing XDC File [C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.srcs/constrs_1/new/contraint_4.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 743.945 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 747.914 ; gain = 436.629
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.458 . Memory (MB): peak = 768.395 ; gain = 20.480

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 14bd1eba3

Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1265.973 ; gain = 497.578

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1462.164 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1462.164 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1462.164 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver.
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver.
INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s).
Phase 4 BUFG optimization | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1462.164 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1462.164 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1462.164 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1462.164 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1462.164 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1462.164 ; gain = 0.000

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.164 ; gain = 0.000

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.164 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 14bd1eba3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1462.164 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1462.164 ; gain = 714.250
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.164 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1462.164 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1/FourBitRegister_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file FourBitRegister_drc_opted.rpt -pb FourBitRegister_drc_opted.pb -rpx FourBitRegister_drc_opted.rpx
Command: report_drc -file FourBitRegister_drc_opted.rpt -pb FourBitRegister_drc_opted.pb -rpx FourBitRegister_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1/FourBitRegister_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.164 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1406452b5

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1462.164 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.164 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 199552633

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.395 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 26841136a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.430 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 26841136a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.432 . Memory (MB): peak = 1468.059 ; gain = 5.895
Phase 1 Placer Initialization | Checksum: 26841136a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.442 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 26841136a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.452 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 2.2 Global Placement Core
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2.2 Global Placement Core | Checksum: 24ab42ac9

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.678 . Memory (MB): peak = 1468.059 ; gain = 5.895
Phase 2 Global Placement | Checksum: 24ab42ac9

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.682 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 24ab42ac9

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.685 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 26567c9cd

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.689 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1de110d53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.695 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1de110d53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.696 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 29e1898b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.808 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 29e1898b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.808 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 29e1898b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.809 . Memory (MB): peak = 1468.059 ; gain = 5.895
Phase 3 Detail Placement | Checksum: 29e1898b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.809 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 29e1898b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.811 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 29e1898b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.818 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 29e1898b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.819 . Memory (MB): peak = 1468.059 ; gain = 5.895

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.059 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 29e1898b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1468.059 ; gain = 5.895
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 29e1898b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1468.059 ; gain = 5.895
Ending Placer Task | Checksum: 1e8590de1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.822 . Memory (MB): peak = 1468.059 ; gain = 5.895
INFO: [Common 17-83] Releasing license: Implementation
43 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.059 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1478.227 ; gain = 10.168
INFO: [Common 17-1381] The checkpoint 'C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1/FourBitRegister_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file FourBitRegister_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1478.227 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file FourBitRegister_utilization_placed.rpt -pb FourBitRegister_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file FourBitRegister_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1478.227 ; gain = 0.000
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
51 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1478.531 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1496.391 ; gain = 17.859
INFO: [Common 17-1381] The checkpoint 'C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1/FourBitRegister_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: f3e9e5b2 ConstDB: 0 ShapeSum: f46f282f RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 12fe8b6d3

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1612.695 ; gain = 107.211
Post Restoration Checksum: NetGraph: f834693f NumContArr: 37b44d94 Constraints: 0 Timing: 0

Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 12fe8b6d3

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1619.277 ; gain = 113.793

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 12fe8b6d3

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1619.277 ; gain = 113.793
 Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 176a86cb4

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 8
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 8
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
 Number of Nodes with overlaps = 0
Phase 3 Initial Routing | Checksum: 162b36798

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
Phase 4.1 Global Iteration 0 | Checksum: 162b36798

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059
Phase 4 Rip-up And Reroute | Checksum: 162b36798

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059

Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 162b36798

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: 162b36798

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059
Phase 6 Post Hold Fix | Checksum: 162b36798

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0121673 %
  Global Horizontal Routing Utilization  = 0.00160581 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 18.018%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0

Phase 7 Route finalize | Checksum: 162b36798

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 162b36798

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 162b36798

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1639.543 ; gain = 134.059

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
61 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:19 . Memory (MB): peak = 1639.543 ; gain = 143.152
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1639.543 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1644.027 ; gain = 4.484
INFO: [Common 17-1381] The checkpoint 'C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1/FourBitRegister_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file FourBitRegister_drc_routed.rpt -pb FourBitRegister_drc_routed.pb -rpx FourBitRegister_drc_routed.rpx
Command: report_drc -file FourBitRegister_drc_routed.rpt -pb FourBitRegister_drc_routed.pb -rpx FourBitRegister_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1/FourBitRegister_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file FourBitRegister_methodology_drc_routed.rpt -pb FourBitRegister_methodology_drc_routed.pb -rpx FourBitRegister_methodology_drc_routed.rpx
Command: report_methodology -file FourBitRegister_methodology_drc_routed.rpt -pb FourBitRegister_methodology_drc_routed.pb -rpx FourBitRegister_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1/FourBitRegister_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file FourBitRegister_power_routed.rpt -pb FourBitRegister_power_summary_routed.pb -rpx FourBitRegister_power_routed.rpx
Command: report_power -file FourBitRegister_power_routed.rpt -pb FourBitRegister_power_summary_routed.pb -rpx FourBitRegister_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
73 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file FourBitRegister_route_status.rpt -pb FourBitRegister_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file FourBitRegister_timing_summary_routed.rpt -pb FourBitRegister_timing_summary_routed.pb -rpx FourBitRegister_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file FourBitRegister_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file FourBitRegister_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file FourBitRegister_bus_skew_routed.rpt -pb FourBitRegister_bus_skew_routed.pb -rpx FourBitRegister_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sun Jun 22 12:03:31 2025...
#-----------------------------------------------------------
# Vivado v2019.2 (64-bit)
# SW Build 2708876 on Wed Nov  6 21:40:23 MST 2019
# IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
# Start of session at: Sun Jun 22 12:03:58 2025
# Process ID: 14064
# Current directory: C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1
# Command line: vivado.exe -log FourBitRegister.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FourBitRegister.tcl -notrace
# Log file: C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1/FourBitRegister.vdi
# Journal file: C:/Jah/EEL470/Assignment 4-Part1 project/Assignment 4-Part1 project.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source FourBitRegister.tcl -notrace
Command: open_checkpoint FourBitRegister_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 296.516 ; gain = 0.000
INFO: [Device 21-403] Loading part xc7z020clg400-1
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 630.570 ; gain = 0.000
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1267.500 ; gain = 14.543
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 1267.500 ; gain = 14.543
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1267.500 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876
open_checkpoint: Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 1267.500 ; gain = 970.984
Command: write_bitstream -force FourBitRegister.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./FourBitRegister.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1735.582 ; gain = 468.082
INFO: [Common 17-206] Exiting Vivado at Sun Jun 22 12:04:25 2025...
