Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
| Date             : Sun Jun 22 12:03:31 2025
| Host             : Balerion running 64-bit major release  (build 9200)
| Command          : report_power -file FourBitRegister_power_routed.rpt -pb FourBitRegister_power_summary_routed.pb -rpx FourBitRegister_power_routed.rpx
| Design           : FourBitRegister
| Device           : xc7z020clg400-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 3.185        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 2.995        |
| Device Static (W)        | 0.190        |
| Effective TJA (C/W)      | 11.5         |
| Max Ambient (C)          | 48.3         |
| Junction Temperature (C) | 61.7         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------+-----------+----------+-----------+-----------------+
| On-Chip      | Power (W) | Used     | Available | Utilization (%) |
+--------------+-----------+----------+-----------+-----------------+
| Slice Logic  |     0.007 |        7 |       --- |             --- |
|   BUFG       |     0.006 |        1 |        32 |            3.13 |
|   Register   |     0.001 |        4 |    106400 |           <0.01 |
|   Others     |     0.000 |        2 |       --- |             --- |
| Signals      |     0.054 |       10 |       --- |             --- |
| I/O          |     2.935 |        9 |       125 |            7.20 |
| Static Power |     0.190 |          |           |                 |
| Total        |     3.185 |          |           |                 |
+--------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.111 |       0.081 |      0.030 |
| Vccaux    |       1.800 |     0.129 |       0.107 |      0.022 |
| Vcco33    |       3.300 |     0.826 |       0.825 |      0.001 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.002 |       0.000 |      0.002 |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccpint   |       1.000 |     0.054 |       0.000 |      0.054 |
| Vccpaux   |       1.800 |     0.010 |       0.000 |      0.010 |
| Vccpll    |       1.800 |     0.003 |       0.000 |      0.003 |
| Vcco_ddr  |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco_mio0 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco_mio1 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                             |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                                    |
| Clock nodes activity        | Low        | User specified less than 75% of clocks                 | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
| Internal nodes activity     | High       | User specified more than 25% of internal nodes         |                                                                                                                    |
| Device models               | High       | Device models are Production                           |                                                                                                                    |
|                             |            |                                                        |                                                                                                                    |
| Overall confidence level    | Low        |                                                        |                                                                                                                    |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+-----------------+-----------+
| Name            | Power (W) |
+-----------------+-----------+
| FourBitRegister |     2.995 |
+-----------------+-----------+


