### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2708876
date_generated | Thu Jun 26 09:58:08 2025 | os_platform | WIN64
product_version | Vivado v2019.2 (64-bit) | project_id | 705eff953fc9479aaccd986969566596
project_iteration | 4 | random_id | 1f1b497c70e95691a8a301c69c46f316
registration_id | 1f1b497c70e95691a8a301c69c46f316 | route_design | TRUE
target_device | xc7z020 | target_family | zynq
target_package | clg400 | target_speed | -1
tool_flow | Vivado

user_environment
cpu_name | 12th Gen Intel(R) Core(TM) i5-12400F | cpu_speed | 2496 MHz
os_name | Windows Server 2016 or Windows 10 | os_release | major release (build 9200)
system_ram | 16.000 GB | total_processors | 1

vivado_usage

gui_handlers
abstractcombinedpanel_add_element=5 | addsrcwizard_specify_hdl_netlist_block_design=1 | addsrcwizard_specify_or_create_constraint_files=1 | basedialog_cancel=4
basedialog_ok=43 | cmdmsgdialog_ok=1 | constraintschooserpanel_create_file=1 | createconstraintsfilepanel_file_name=1
createsrcfiledialog_file_name=1 | createsrcfiledialog_file_type=1 | definemodulesdialog_define_modules_and_specify_io_ports=22 | exprunproppanels_constraints=1
expruntreepanel_exp_run_tree_table=2 | filesetpanel_file_set_panel_tree=30 | flownavigatortreepanel_flow_navigator_tree=16 | fpgachooser_family=1
fpgachooser_fpga_table=1 | fpgachooser_package=1 | fpgachooser_speed=1 | gettingstartedview_create_new_project=1
pacommandnames_add_sources=2 | pacommandnames_open_hardware_manager=2 | pacommandnames_open_target_wizard=2 | pacommandnames_reports_window=1
pacommandnames_run_bitgen=6 | pacommandnames_simulation_run_behavioral=1 | paviews_project_summary=2 | programdebugtab_open_recently_opened_target=3
programdebugtab_open_target=2 | programdebugtab_program_device=6 | programdebugtab_refresh_device=3 | programfpgadialog_program=5
projectnamechooser_project_name=1 | srcchooserpanel_create_file=1 | syntheticagettingstartedview_recent_projects=2 | syntheticastatemonitor_cancel=1

java_command_handlers
addsources=3 | launchopentarget=2 | launchprogramfpga=6 | newproject=1
openhardwaremanager=2 | refreshdevice=3 | runbitgen=6 | runimplementation=7
runsynthesis=8 | showview=1 | simulationrun=1 | toolssettings=1
toolstemplates=1 | viewtaskrtlanalysis=1 | viewtasksimulation=1

other_data
guimode=2

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=0 | export_simulation_ies=0
export_simulation_modelsim=0 | export_simulation_questa=0 | export_simulation_riviera=0 | export_simulation_vcs=0
export_simulation_xsim=0 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=1 | simulator_language=Mixed | srcsetcount=1 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=1 | totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 | fdce=3 | ibuf=5 | lut3=2
lut4=1 | lut6=3 | obuf=2
pre_unisim_transformation
bufg=1 | fdce=3 | ibuf=5 | lut3=2
lut4=1 | lut6=3 | obuf=2

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] | -bram_register_opt=default::[not_specified] | -clock_opt=default::[not_specified] | -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] | -directive=default::[not_specified] | -dsp_register_opt=default::[not_specified] | -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] | -hold_fix=default::[not_specified] | -insert_negative_edge_ffs=default::[not_specified] | -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] | -restruct_opt=default::[not_specified] | -retime=default::[not_specified] | -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] | -uram_register_opt=default::[not_specified] | -verbose=default::[not_specified] | -vhfn=default::[not_specified]

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
zps7-1=1

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=1 | bufgctrl_util_percentage=3.13
bufhce_available=72 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=16 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=8 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=16 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=4 | mmcme2_adv_fixed=0 | mmcme2_adv_used=0 | mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsps_available=220 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=0 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 | block_ram_tile_fixed=0 | block_ram_tile_used=0 | block_ram_tile_util_percentage=0.00
ramb18_available=280 | ramb18_fixed=0 | ramb18_used=0 | ramb18_util_percentage=0.00
ramb36_fifo_available=140 | ramb36_fifo_fixed=0 | ramb36_fifo_used=0 | ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock | bufg_used=1 | fdce_functional_category=Flop & Latch | fdce_used=3
ibuf_functional_category=IO | ibuf_used=5 | lut3_functional_category=LUT | lut3_used=2
lut4_functional_category=LUT | lut4_used=1 | lut6_functional_category=LUT | lut6_used=3
obuf_functional_category=IO | obuf_used=2
slice_logic
f7_muxes_available=26600 | f7_muxes_fixed=0 | f7_muxes_used=0 | f7_muxes_util_percentage=0.00
f8_muxes_available=13300 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_logic_available=53200 | lut_as_logic_fixed=0 | lut_as_logic_used=5 | lut_as_logic_util_percentage=<0.01
lut_as_memory_available=17400 | lut_as_memory_fixed=0 | lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=106400 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=3 | register_as_flip_flop_util_percentage=<0.01
register_as_latch_available=106400 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=53200 | slice_luts_fixed=0 | slice_luts_used=5 | slice_luts_util_percentage=<0.01
slice_registers_available=106400 | slice_registers_fixed=0 | slice_registers_used=3 | slice_registers_util_percentage=<0.01
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=53200 | lut_as_logic_fixed=0
lut_as_logic_used=5 | lut_as_logic_util_percentage=<0.01 | lut_as_memory_available=17400 | lut_as_memory_fixed=0
lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
register_driven_from_outside_the_slice_fixed=0 | register_driven_from_outside_the_slice_used=0 | register_driven_from_within_the_slice_fixed=0 | register_driven_from_within_the_slice_used=3
slice_available=13300 | slice_fixed=0 | slice_registers_available=106400 | slice_registers_fixed=0
slice_registers_used=3 | slice_registers_util_percentage=<0.01 | slice_used=2 | slice_util_percentage=0.02
slicel_fixed=0 | slicel_used=1 | slicem_fixed=0 | slicem_used=1
unique_control_sets_available=13300 | unique_control_sets_fixed=13300 | unique_control_sets_used=1 | unique_control_sets_util_percentage=<0.01
using_o5_and_o6_fixed=<0.01 | using_o5_and_o6_used=1 | using_o5_output_only_fixed=1 | using_o5_output_only_used=0
using_o6_output_only_fixed=0 | using_o6_output_only_used=4
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7z020clg400-1
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=CodeGenerator | -verilog_define=default::[not_specified]
usage
elapsed=00:00:21s | hls_ip=0 | memory_gain=710.172MB | memory_peak=1039.668MB

xsim
command_line_options
-sim_mode=default::behavioral | -sim_type=default::