library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Testbench entity has no ports
entity tb_read_image_vhdl is
end tb_read_image_vhdl;

architecture behavior of tb_read_image_vhdl is

  -- Component declaration for the Unit Under Test (UUT)
  component read_image_VHDL
    port (
      clock     : in std_logic;
      data      : in std_logic_vector(7 downto 0);
      rdaddress : in std_logic_vector(3 downto 0);
      wraddress : in std_logic_vector(3 downto 0);
      we        : in std_logic;
      re        : in std_logic;
      q         : out std_logic_vector(7 downto 0)
    );
  end component;

  -- Signal declarations to connect to UUT
  signal clock     : std_logic := '0';
  signal data      : std_logic_vector(7 downto 0) := (others => '0');
  signal rdaddress : std_logic_vector(3 downto 0) := (others => '0');
  signal wraddress : std_logic_vector(3 downto 0) := (others => '0');
  signal we        : std_logic := '0';
  signal re        : std_logic := '0';
  signal q         : std_logic_vector(7 downto 0);

  -- Clock period definition
  constant clock_period : time := 10 ns;

  -- Loop index for reading memory
  signal i : integer;

begin

  -- Instantiate the Unit Under Test (UUT)
  uut: read_image_VHDL
    port map (
      clock     => clock,
      data      => data,
      rdaddress => rdaddress,
      wraddress => wraddress,
      we        => we,
      re        => re,
      q         => q
    );

  -- Clock generation process
  clock_process : process
  begin
    clock <= '0';
    wait for clock_period / 2;
    clock <= '1';
    wait for clock_period / 2;
  end process;

  -- Stimulus process to read from initialized RAM
  stim_proc: process
  begin
    -- Initial values
    data      <= x"00";
    rdaddress <= x"0";
    wraddress <= x"0";
    we        <= '0';
    re        <= '0';
    wait for 100 ns;

    -- Enable read and loop through all addresses
    re <= '1';
    for i in 0 to 15 loop
      rdaddress <= std_logic_vector(to_unsigned(i, 4));
      wait for 20 ns;
    end loop;

    -- End simulation
    wait;
  end process;

end behavior;
