module traffic_light_controller(
    input clk,
    input reset,
    input farm_sensor,
    output reg ns_green,
    output reg ns_red,
    output reg ew_green,
    output reg ew_red,
    output reg [7:0] ssd_segments
);

    // Clock divider: 100 MHz to 1 Hz
    reg [25:0] clk_div_counter = 0;
    reg clk_1hz = 0;

    always @(posedge clk) begin
        if (clk_div_counter >= 49999999) begin
            clk_div_counter <= 0;
            clk_1hz <= ~clk_1hz;
        end else begin
            clk_div_counter <= clk_div_counter + 1;
        end
    end

    // FSM states
    localparam NS_GREEN   = 3'b000,
               NS_YELLOW  = 3'b001,
               EW_GREEN   = 3'b010,
               EW_YELLOW  = 3'b011;

    reg [2:0] state = NS_GREEN;
    reg [1:0] yellow_timer = 0;
    reg prev_sensor = 0;

    // FSM logic
    always @(posedge clk_1hz or posedge reset) begin
        if (reset) begin
            state <= NS_GREEN;
            yellow_timer <= 0;
            prev_sensor <= 0;
        end else begin
            prev_sensor <= farm_sensor;

            case (state)
                NS_GREEN: begin
                    if (farm_sensor && !prev_sensor) begin // rising edge
                        state <= NS_YELLOW;
                        yellow_timer <= 0;
                    end
                end
                NS_YELLOW: begin
                    if (yellow_timer == 2) begin // 3 seconds
                        state <= EW_GREEN;
                        yellow_timer <= 0;
                    end else begin
                        yellow_timer <= yellow_timer + 1;
                    end
                end
                EW_GREEN: begin
                    if (!farm_sensor && prev_sensor) begin // falling edge
                        state <= EW_YELLOW;
                        yellow_timer <= 0;
                    end
                end
                EW_YELLOW: begin
                    if (yellow_timer == 2) begin // 3 seconds
                        state <= NS_GREEN;
                        yellow_timer <= 0;
                    end else begin
                        yellow_timer <= yellow_timer + 1;
                    end
                end
            endcase
        end
    end

    // Output logic
    always @(*) begin
    // Default all lights off
    ns_green = 0; ns_red = 0;
    ew_green = 0; ew_red = 0;
    ssd_segments = 8'b11111111; // All segments off

    case (state)
        NS_GREEN: begin
            ns_green = 1;
            ew_red = 1;
        end
        NS_YELLOW: begin
            ns_green = 0; // keep green OFF for yellow phase
            ns_red = 0;
            ew_red = 1;
            ssd_segments = 8'b01011011; // Display "2" for yellow
        end
        EW_GREEN: begin
            ew_green = 1;
            ns_red = 1;
        end
        EW_YELLOW: begin
            ew_green = 0; // keep green OFF for yellow phase
            ew_red = 0;
            ns_red = 1;
            ssd_segments = 8'b01011011; // Display "2" for yellow
        end
    endcase
end

endmodule
