### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2708876
date_generated | Fri Aug 1 08:34:09 2025 | os_platform | WIN64
product_version | Vivado v2019.2 (64-bit) | project_id | cabf4c015f9e4f72bc79c252aeb82f17
project_iteration | 15 | random_id | 1f1b497c70e95691a8a301c69c46f316
registration_id | 1f1b497c70e95691a8a301c69c46f316 | route_design | TRUE
target_device | xc7z020 | target_family | zynq
target_package | clg400 | target_speed | -1
tool_flow | Vivado

user_environment
cpu_name | 12th Gen Intel(R) Core(TM) i5-12400F | cpu_speed | 2496 MHz
os_name | Windows Server 2016 or Windows 10 | os_release | major release (build 9200)
system_ram | 16.000 GB | total_processors | 1

vivado_usage

gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1 | addsrcwizard_specify_or_create_constraint_files=1 | addsrcwizard_specify_simulation_specific_hdl_files=1 | basedialog_apply=1
basedialog_cancel=5 | basedialog_ok=41 | basedialog_yes=20 | boardchooser_board_table=2
cmdmsgdialog_ok=1 | constraintschooserpanel_create_file=1 | createconstraintsfilepanel_file_name=1 | createsrcfiledialog_file_name=2
filesetpanel_file_set_panel_tree=82 | flownavigatortreepanel_flow_navigator_tree=64 | graphicalview_zoom_in=13 | graphicalview_zoom_out=32
launchpanel_dont_show_this_dialog_again=1 | logmonitor_monitor=11 | mainmenumgr_edit=2 | mainmenumgr_file=4
mainmenumgr_project=2 | msgtreepanel_message_view_tree=2 | pacommandnames_add_sources=3 | pacommandnames_auto_connect_target=3
pacommandnames_auto_update_hier=1 | pacommandnames_new_project=1 | pacommandnames_open_hardware_manager=5 | pacommandnames_set_as_top=1
pacommandnames_simulation_close=1 | pacommandnames_simulation_live_break=1 | pacommandnames_simulation_live_run=7 | pacommandnames_simulation_live_step=1
pacommandnames_simulation_reset_behavioral=3 | pacommandnames_simulation_run_behavioral=7 | pacommandnames_simulation_settings=2 | paviews_project_summary=10
programdebugtab_open_recently_opened_target=2 | programdebugtab_open_target=3 | programdebugtab_program_device=13 | programdebugtab_refresh_device=1
programfpgadialog_program=14 | projectnamechooser_project_name=1 | projectsettingssimulationpanel_tabbed_pane=4 | rdicommands_undo=4
rdiviews_waveform_viewer=6 | rungadget_show_warning_and_error_messages_in_messages=1 | simulationliverunforcomp_specify_time_and_units=4 | simulationobjectspanel_simulation_objects_tree_table=3
srcchooserpanel_create_file=2 | srcmenu_ip_hierarchy=1 | syntheticagettingstartedview_recent_projects=3 | waveformnametree_waveform_name_tree=11

java_command_handlers
addsources=4 | autoconnecttarget=3 | closeproject=1 | fliptoviewtaskimplementation=1
launchprogramfpga=14 | newproject=1 | openhardwaremanager=8 | programdevice=1
runbitgen=21 | settopnode=1 | showview=8 | simulationbreak=1
simulationclose=1 | simulationrun=10 | simulationrunfortime=6 | toolssettings=2
viewtaskimplementation=1 | viewtaskprojectmanager=2

other_data
guimode=4

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=0 | export_simulation_ies=0
export_simulation_modelsim=0 | export_simulation_questa=0 | export_simulation_riviera=0 | export_simulation_vcs=0
export_simulation_xsim=0 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=7 | simulator_language=Mixed | srcsetcount=1 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=1 | totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 | carry4=7 | fdce=5 | fdre=27
gnd=1 | ibuf=3 | lut1=3 | lut2=3
lut3=1 | lut4=4 | lut5=1 | lut6=5
obuf=12 | vcc=1
pre_unisim_transformation
bufg=1 | carry4=7 | fdce=5 | fdre=27
gnd=1 | ibuf=3 | lut1=3 | lut2=3
lut3=1 | lut4=4 | lut5=1 | lut6=5
obuf=12 | vcc=1

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] | -bram_register_opt=default::[not_specified] | -clock_opt=default::[not_specified] | -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] | -directive=default::[not_specified] | -dsp_register_opt=default::[not_specified] | -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] | -hold_fix=default::[not_specified] | -insert_negative_edge_ffs=default::[not_specified] | -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] | -restruct_opt=default::[not_specified] | -retime=default::[not_specified] | -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] | -uram_register_opt=default::[not_specified] | -verbose=default::[not_specified] | -vhfn=default::[not_specified]

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] | -waived=default::[not_specified]
results
timing-17=32

report_power
command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -hierarchical_depth=default::4 | -l=default::[not_specified] | -name=default::[not_specified]
-no_propagation=default::[not_specified] | -return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified]
-vid=default::[not_specified] | -xpe=default::[not_specified]
usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) | board_selection=medium (10"x10") | confidence_level_clock_activity=Low | confidence_level_design_state=High
confidence_level_device_models=High | confidence_level_internal_activity=Medium | confidence_level_io_activity=Low | confidence_level_overall=Low
customer=TBD | customer_class=TBD | devstatic=0.277716 | die=xc7z020clg400-1
dsp_output_toggle=12.500000 | dynamic=4.320798 | effective_thetaja=11.5 | enable_probability=0.990000
family=zynq | ff_toggle=12.500000 | flow_state=routed | heatsink=none
i/o=4.104465 | input_toggle=12.500000 | junction_temp=78.0 (C) | logic=0.083491
mgtavcc_dynamic_current=0.000000 | mgtavcc_static_current=0.000000 | mgtavcc_total_current=0.000000 | mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000 | mgtavtt_static_current=0.000000 | mgtavtt_total_current=0.000000 | mgtavtt_voltage=1.200000
mgtvccaux_dynamic_current=0.000000 | mgtvccaux_static_current=0.000000 | mgtvccaux_total_current=0.000000 | mgtvccaux_voltage=1.800000
netlist_net_matched=NA | off-chip_power=0.000000 | on-chip_power=4.598515 | output_enable=1.000000
output_load=5.000000 | output_toggle=12.500000 | package=clg400 | pct_clock_constrained=0.000000
pct_inputs_defined=0 | platform=nt64 | process=typical | ram_enable=50.000000
ram_write=50.000000 | read_saif=False | set/reset_probability=0.000000 | signal_rate=False
signals=0.132843 | simulation_file=None | speedgrade=-1 | static_prob=False
temp_grade=commercial | thetajb=7.4 (C/W) | thetasa=0.0 (C/W) | toggle_rate=False
user_board_temp=25.0 (C) | user_effective_thetaja=11.5 | user_junc_temp=78.0 (C) | user_thetajb=7.4 (C/W)
user_thetasa=0.0 (C/W) | vccadc_dynamic_current=0.000000 | vccadc_static_current=0.020000 | vccadc_total_current=0.020000
vccadc_voltage=1.800000 | vccaux_dynamic_current=0.150112 | vccaux_io_dynamic_current=0.000000 | vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 | vccaux_io_voltage=1.800000 | vccaux_static_current=0.032416 | vccaux_total_current=0.182528
vccaux_voltage=1.800000 | vccbram_dynamic_current=0.000000 | vccbram_static_current=0.004093 | vccbram_total_current=0.004093
vccbram_voltage=1.000000 | vccint_dynamic_current=0.224333 | vccint_static_current=0.058036 | vccint_total_current=0.282369
vccint_voltage=1.000000 | vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000 | vcco12_total_current=0.000000
vcco12_voltage=1.200000 | vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000 | vcco135_total_current=0.000000
vcco135_voltage=1.350000 | vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000 | vcco15_total_current=0.000000
vcco15_voltage=1.500000 | vcco18_dynamic_current=0.000000 | vcco18_static_current=0.000000 | vcco18_total_current=0.000000
vcco18_voltage=1.800000 | vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000 | vcco25_total_current=0.000000
vcco25_voltage=2.500000 | vcco33_dynamic_current=1.159474 | vcco33_static_current=0.001000 | vcco33_total_current=1.160474
vcco33_voltage=3.300000 | vcco_ddr_dynamic_current=0.000000 | vcco_ddr_static_current=0.000000 | vcco_ddr_total_current=0.000000
vcco_ddr_voltage=1.500000 | vcco_mio0_dynamic_current=0.000000 | vcco_mio0_static_current=0.000000 | vcco_mio0_total_current=0.000000
vcco_mio0_voltage=1.800000 | vcco_mio1_dynamic_current=0.000000 | vcco_mio1_static_current=0.000000 | vcco_mio1_total_current=0.000000
vcco_mio1_voltage=1.800000 | vccpaux_dynamic_current=0.000000 | vccpaux_static_current=0.010330 | vccpaux_total_current=0.010330
vccpaux_voltage=1.800000 | vccpint_dynamic_current=0.000000 | vccpint_static_current=0.093945 | vccpint_total_current=0.093945
vccpint_voltage=1.000000 | vccpll_dynamic_current=0.000000 | vccpll_static_current=0.003000 | vccpll_total_current=0.003000
vccpll_voltage=1.800000 | version=2019.2

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=1 | bufgctrl_util_percentage=3.13
bufhce_available=72 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=16 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=8 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=16 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=4 | mmcme2_adv_fixed=0 | mmcme2_adv_used=0 | mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsps_available=220 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=0 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 | block_ram_tile_fixed=0 | block_ram_tile_used=0 | block_ram_tile_util_percentage=0.00
ramb18_available=280 | ramb18_fixed=0 | ramb18_used=0 | ramb18_util_percentage=0.00
ramb36_fifo_available=140 | ramb36_fifo_fixed=0 | ramb36_fifo_used=0 | ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock | bufg_used=1 | carry4_functional_category=CarryLogic | carry4_used=7
fdce_functional_category=Flop & Latch | fdce_used=5 | fdre_functional_category=Flop & Latch | fdre_used=27
ibuf_functional_category=IO | ibuf_used=3 | lut1_functional_category=LUT | lut1_used=3
lut2_functional_category=LUT | lut2_used=3 | lut3_functional_category=LUT | lut3_used=1
lut4_functional_category=LUT | lut4_used=4 | lut5_functional_category=LUT | lut5_used=1
lut6_functional_category=LUT | lut6_used=5 | obuf_functional_category=IO | obuf_used=12
slice_logic
f7_muxes_available=26600 | f7_muxes_fixed=0 | f7_muxes_used=0 | f7_muxes_util_percentage=0.00
f8_muxes_available=13300 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_logic_available=53200 | lut_as_logic_fixed=0 | lut_as_logic_used=15 | lut_as_logic_util_percentage=0.03
lut_as_memory_available=17400 | lut_as_memory_fixed=0 | lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=106400 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=32 | register_as_flip_flop_util_percentage=0.03
register_as_latch_available=106400 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=53200 | slice_luts_fixed=0 | slice_luts_used=15 | slice_luts_util_percentage=0.03
slice_registers_available=106400 | slice_registers_fixed=0 | slice_registers_used=32 | slice_registers_util_percentage=0.03
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=53200 | lut_as_logic_fixed=0
lut_as_logic_used=15 | lut_as_logic_util_percentage=0.03 | lut_as_memory_available=17400 | lut_as_memory_fixed=0
lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 | lut_in_front_of_the_register_is_unused_used=0 | lut_in_front_of_the_register_is_used_fixed=0 | lut_in_front_of_the_register_is_used_used=1
register_driven_from_outside_the_slice_fixed=1 | register_driven_from_outside_the_slice_used=1 | register_driven_from_within_the_slice_fixed=1 | register_driven_from_within_the_slice_used=31
slice_available=13300 | slice_fixed=0 | slice_registers_available=106400 | slice_registers_fixed=0
slice_registers_used=32 | slice_registers_util_percentage=0.03 | slice_used=15 | slice_util_percentage=0.11
slicel_fixed=0 | slicel_used=14 | slicem_fixed=0 | slicem_used=1
unique_control_sets_available=13300 | unique_control_sets_fixed=13300 | unique_control_sets_used=3 | unique_control_sets_util_percentage=0.02
using_o5_and_o6_fixed=0.02 | using_o5_and_o6_used=2 | using_o5_output_only_fixed=2 | using_o5_output_only_used=0
using_o6_output_only_fixed=0 | using_o6_output_only_used=13
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7z020clg400-1
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=traffic_light_controller | -verilog_define=default::[not_specified]
usage
elapsed=00:00:22s | hls_ip=0 | memory_gain=704.297MB | memory_peak=1169.102MB

xsim
command_line_options
-sim_mode=default::behavioral | -sim_type=default::