module top_image_processor (
    input wire clk,
    input wire rst,
    output wire [7:0] red_out,
    output wire [7:0] green_out,
    output wire [7:0] blue_out
);

    reg [18:0] addr;

    wire [7:0] red, green, blue;

    // Instantiate RAMs
    red_ram u_red (.clk(clk), .addr(addr), .data_out(red));
    green_ram u_green (.clk(clk), .addr(addr), .data_out(green));
    blue_ram u_blue (.clk(clk), .addr(addr), .data_out(blue));

    // Address generator
    always @(posedge clk or posedge rst) begin
        if (rst)
            addr <= 0;
        else if (addr < 307199)
            addr <= addr + 1;
        else
            addr <= 0;
    end

    assign red_out = red;
    assign green_out = green;
    assign blue_out = blue;

endmodule
