module red_ram (
    input wire clk,
    input wire [ADDR_WIDTH-1:0] addr,
    output reg [7:0] data_out
);
    reg [7:0] memory [0:IMG_SIZE-1];

    initial begin
        $readmemh("red.mem", memory);
    end

    always @(posedge clk) begin
        data_out <= memory[addr];
    end
endmodule
